EECS 140 Four Bit Adder

Adder with Display

Objectives

The objective of this laboratory exercise is for you to learn how to use modular design in VHDL to create a real world application by implementing an adder unit into an FPGA chip and display the addition result.

You will use Altera's Quartus software to implement a 4-bit adder circuit. You will then connect the result of the adder to the input of your display driver (from the previous lab). Finally, you will download the circuit design to the board and will test proper functionality of the circuit. An eight bit dip switch will be used for implementing two 4-bit numbers, the addition will be outputted on the seven segment LEDs.

Discussion

For this lab, you will use the Flex chip with predefined pin assignments on the Altera UP2 development board. The concept is to design and implement an adder, which will have the ability to take two 4-bit binary numbers and output its 8-bit addition result. You will use a seven-segment display to display the binary output in hexadecimal format. Your inputs will range from the hexadecimal numbers 0 to F. Likewise, your outputs will range from 00 to 1E.

We will also introduce modular design for VHDL. This is a powerful tool to streamline FPGA design, avoid code repetition and enhance portability, reusability and abstraction.

Tasks

Quiz

Please answer the following questions and submit to your TA at the start of the lab:

1. (Previous Lab) Why did we have to negate the outputs of the seven segment display?
2. If we wanted the display to light up the left seven segment LEDs instead of the right ones, what would we change?
3. (Current Lab) What's the basic component we will use to implement our 4-bit adder?
4. What kind of 4-bit adder are we designing?
5. How will we output the result of the addition?

Step 1: VHDL Tutorials

If you haven't done so yet, review the following tutorials for VHDL, FPGAs and Quartus. Pay special attention the the modular VHDL tutorial, as from now on we will use modular VHDL almost exclusively.

• This VHDL tutorial will teach about the VHDL language, its fundamentals, and how to represent a simple circuit in VHDL.
• This Modular VHDL tutorial will teach about the using components in VHDL, and creating larger entities by structural design.
• This Altera Quartus II tutorial will teach about using this program to write, simulate, implement and download your circuits into an FPGA.

Step 2: Ripple Carry Adder Design

You should have a good idea of the adder design concept as well as some basic VHDL. The main approach is to start little, then build big. Hence:

• Create a new entity for a 1-bit Full Adder. Use the classic truth table, Kmap, Sum-Of-Products approach to get the equations for your outputs.
• Simulate for all input combinations, and make sure there are no mistakes
• Do not download to the board, since we have nothing to display (yet)
• Draw the circuit for creating a 4-bit ripple carry adder from multiple Full Adders.
• Once your block diagram, including all components and signals inside your ripple carry adder, is ready, identify which parts will make up the entity, identify the components, and finally count all the intermediate signals and give them appropriate names.
• Use your 1-bit adder as a component to a new VHDL entity for a 4-bit ripple carry adder. The Modular VHDL tutorial shows an example multi-bit XOR gate made out of smaller XOR components in VHDL.

Step 3: Structural VHDL

Write VHDL code for your circuit in Quartus. Follow the structural/modular method of programming. Be very careful in mapping ports when doing component instantiation. Once the adder is done you will need to simulate it to check whether it is outputting the right values.

Step 4: Simulation

Once you have written your VHDL description of how the circuit should behave you should save and simulate. Compile and simulate each component individually at first. Check the waveform against what the value of a given function should be. If you have errors that need to be debugged, use the simulator to determine which outputs are not working correctly. Look at the output waveform and compare it to the truth tables for 7-segment output. Trace your design and fix any description errors. Consult your T.A. if needed.

Step 5: Adder with Display

Once your circuit simulates correctly, create a new entity 'adder_with_display' that will use your ripple carry adder as a component. This new entity will also use your display driver as a component. Declare each component, declare the signals that will connect them, instantiate the components and do a port map to connect them to inputs, outputs or signals.

Step 6: Download to the Board

Once your new entity compiles and simulates, assign pins to your entity's inputs and outputs. Use the pin assignment table in Figure 3. You want to assign your adder's input 1 to Flex_Switch[1-4] and input 2 to Flex_Switch[5-8]. Assign the appropriate pins of your display to either the Most Significant Display(MSD) or the Least Significant Display(LSD) seven segment LED pins.

Figure 3: Flex Chip Pin Assignments

You will program the board as you did in the first laboratory exercise. Go the Quartus programmer and make sure the board is correctly powered and the Byte Blaster parallel cable is properly connected to the PC you are using. If you have any troubles consult your TA.

Step 7: Evaluate and Correct

Now you will want to verify that the board is operating correctly. Change inputs using the dip switch and make sure that you get the correct corresponding output. If you get incorrect outputs retrace your steps making sure you have correct pin assignments and that your VHDL is correct. After you've tested circuit for proper operation, show it to your TA.

Lab Report

Now write your lab report according the format your TA has outlined for you. Make sure to include into your lab report any possibilities of improvements to your circuits or ways you believe it could have been implemented better.