EECS 140 Introduction StructuralVHDL

Introduction to Structural VHDL

PreLab

Google about VHDL Component Declaration, Signal Declaration and Component Instantiation/port mapping

Objective

Introduction to  modular design for VHDL. This is a powerful tool to streamline 
FPGA design, avoid code repetition and enhance portability, re-usability and abstraction.

NOTE: Pay very close attention to 3 topics here: Component Declaration, Signal Declaration and Component Instantiation

Testbench Generator Website

https://www.doulos.com/knowhow/perl/testbench_creation/

You will read through the tutorial provided above and implement these designs in Vivado.

Note: You will need to create new project in H:// (as in the earlier labs) and provide these details:

 Family: Artix-7, Package: CPG236, Speed: -1 Part: xc7a35tcpg236-1

XDC file for toplevel

You need to create a new XDC file for the top level inputs and outputs. Click here for Basys3 Constraints

Lab Report

Now write your lab report according the format your TA has outlined for you. Provide ALL VHDL scripts you worked on in Vivado.