-- Unsigned 4 bit multiplier
-- <PUT YOUR NAME HERE>

library ieee;
use ieee.std_logic_1164.all;

ENTITY multiplier IS
	-- No carry in or carry out for demonstration purposes
	PORT (
		Q        : IN  STD_LOGIC_VECTOR(3 downto 0);
		M        : IN  STD_LOGIC_VECTOR(3 downto 0);
		Result   : OUT STD_LOGIC_VECTOR(7 downto 0)
	);
END multiplier;

ARCHITECTURE Structural of multiplier is

	-- Declare all signals and components here
	SIGNAL Dummy_Signal         : STD_LOGIC;
	SIGNAL Dummy_Signal_Vector  : STD_LOGIC_VECTOR (3 downto 0);
BEGIN

	-- Connect values to all outputs and components here, through instantiation or assignment
	Result   <= "01010101"; -- This is obviously a dummy assignment. Replace it.

END Structural;