-- 4 bit 4-to-1 multiplexer
-- Jorge Ortiz, University of Kansas
-- Created for EECS 140 Lab 6

library ieee;
use ieee.std_logic_1164.all;

ENTITY MUXer IS
	-- No carry in or carry out for demonstration purposes
	PORT (
        Input0       		: IN  STD_LOGIC_VECTOR(3 downto 0);
        Input1       		: IN  STD_LOGIC_VECTOR(3 downto 0);
        Input2       		: IN  STD_LOGIC_VECTOR(3 downto 0);
        Input3       		: IN  STD_LOGIC_VECTOR(3 downto 0);
        Control       		: IN  STD_LOGIC_VECTOR(1 downto 0);
        Output     		: OUT STD_LOGIC_VECTOR(3 downto 0)
	);
END MUXer;

ARCHITECTURE Procedural of MUXer IS

BEGIN

	PROCESS (Input0, Input1, Input2, Input3, Control)
	BEGIN
		CASE Control is
			when "00"   => Output <= Input0;
			when "01"   => Output <= Input1;
			when "10"   => Output <= Input2;
			when others => Output <= Input3;
		END CASE;
	END PROCESS;

END Procedural;