-- Unsigned 4 bit OR
-- Jorge Ortiz, University of Kansas
-- Created for EECS 140 Lab 6

library ieee;
use ieee.std_logic_1164.all;

ENTITY ORer IS
	-- No carry in or carry out for demonstration purposes
	PORT (
        X       		: IN  STD_LOGIC_VECTOR(3 downto 0);
        Y       		: IN  STD_LOGIC_VECTOR(3 downto 0);
        Or_Result     		: OUT STD_LOGIC_VECTOR(3 downto 0)
	);
END ORer;

ARCHITECTURE Behavioral of ORer is


BEGIN

	Or_Result(3 downto 0)	<= X OR Y;

END Behavioral;