-- Unsigned 4 bit AND
-- Jorge Ortiz, University of Kansas
-- Created for EECS 140 Lab 6

library ieee;
use ieee.std_logic_1164.all;

ENTITY ANDer IS
	-- No carry in or carry out for demonstration purposes
	PORT (
        A       		: IN  STD_LOGIC_VECTOR(3 downto 0);
        B       		: IN  STD_LOGIC_VECTOR(3 downto 0);
        And_Result     		: OUT STD_LOGIC_VECTOR(3 downto 0)
	);
END ANDer;

ARCHITECTURE Behavioral of ANDer is


BEGIN

	And_Result(3 downto 0)	<= A AND B;

END Behavioral;