-- MAX+plus II VHDL Template
-- Clearable loadable enablable counter

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY fourbitcounter IS
	PORT
	(
		Initial_Value	: IN	STD_LOGIC_VECTOR(3 downto 0);
		Clock			: IN	STD_LOGIC;
		Clear_n			: IN	STD_LOGIC;
		Enable			: IN	STD_LOGIC;
		Load_n			: IN	STD_LOGIC;
		Counter_Output	: OUT 	STD_LOGIC_VECTOR(3 downto 0)
	);

END fourbitcounter;

ARCHITECTURE a OF fourbitcounter IS

	SIGNAL	Counter_signal	: STD_LOGIC_VECTOR(31 downto 0); -- 32 bit internal signal
	
BEGIN

	PROCESS (Clock, Clear_n)
	BEGIN
		IF Clear_n = '0' THEN
			Counter_signal <= (others=>'0'); -- Clear resets to Zero			
		ELSIF (Clock'EVENT AND Clock = '1') THEN
			IF Load_n = '0' THEN
				Counter_signal(27 downto 24) <= Initial_Value; -- Load resets to inital value
			ELSE
				IF Enable = '1' THEN
					Counter_signal <= Counter_signal + 1; -- Counter updates every clock cycle @ 25Mhxz
				ELSE
					Counter_signal <= Counter_signal; -- But only if enabled
				END IF;
			END IF;
		END IF;
	END PROCESS;

	Counter_Output <= Counter_signal(27 downto 24);  -- The output of the counter are some of the most significant bits
	
END a;