Implementation of nuclear power plant control circuit

Objective:

The goal of this lab exercise is to;

1. work with slightly more complex logic networks
2. independently design the logic circuit in VHDL
3. troubleshoot design by reading console error messages
4. implementing design on Basys3 board
5. validate results using originally written Truth Table

Problem Statement:

Adam is delighted!!! He secured a job as a “Digital Design Engineer” in a Nuclear Power Plant. The nuclear plant has four sensors placed in four dangerous zones. These sensors indicate any impending danger which enables the maintenance officer to shut down the plant. Out of the four, three major sensors are namely X, Y, and Z. If any of the two-out of three major sensors-sense some danger, they actuate an alarm that notifies the maintenance officer for a plant shutdown. However, there is a small caveat. If sensor Z is one of the two major sensors that triggered an alarm, the maintenance officer shuts the plant only if another sensor (minor), “sensor B”, associated with sensor Z also sounds the alarm.

Adam had to dust his Boolean algebra skills to design the truth table that outputs a variable S which indicates when the plant has to shut down. He also has to provide a schematic capture of the same that helps the maintenance officer to understand the conditions for the plant shutdown. Imagine “U” were Adam, and provide a viable solution.

Pre-lab work:

1. Draw the Boolean Logic Network for above problem statement
2. Write the truth table for the same.
3. Specify the type of gate and quantity for question 1
4. What does Parse Error in VHDL mean?
5. What is the significance of Xilinx Design Constraints file (XDC) in generating a programming file?

Practical Steps Involved:

• Create a new VHDL Program within a new project in Vivado to design the Expression derived from the problem statement.

'AND' keyword in VHDL is to represent '.' (and gate) operation in Boolean Expression.
'OR' keyword in VHDL is to represent '+' (or gate) operation in Boolean Expression.
'NOT' keyword in VHDL is to represent 'Apostrophe' (not gate) operation in Boolean Expression.

• Use the same options for the target device when creating a new project.
• Note: Please save your work on H drive.
• If you need help to get started with Vivado and implementation of the boolean expression, please look through the tutorial we went through in the lab 1.
• Introduction to Vivado Tutorial to access the tutorial of lab 1.
• Basys3_Constraints to access the constraints file.

Test your design:

Using the slide switches and the output LED, verify your design by cross checking with the truth table for the expression.

Lab Report:

Write your lab report per instructions from you TA. In your lab report, make certain to paste snapshots of your schematic, simulation, XDC file and also include Truthtable.