UART-LITE Information:
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Source:
Xilinx OPB UART Lite Documentation
http://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_uartlite.pdf

Important memory offsets:
UART_RX_FIFO        offset is 0x0   (Used to read Rx_FIFO values, read-only)
UART_TX_FIFO        offset is 0x4   (Used to write Tx_FIFO values, write-only)
UART_STATUS_REG     offset is 0x8   (Used to check UART status, read-only)
UART_CONTROL_REG    offset is 0x12  (Used to configure UART, write-only)

Important bit-masks:
TX_FIFO_FULL    8   (Used to check if the Tx_FIFO is full)
TX_FIFO_EMPTY   4   (Used to check if the Tx_FIFO is empty)
RX_FIFO_FULL    2   (Used to check if the Rx_FIFO is full)
RX_FIFO_VALID   1   (Used to check if the Rx_FIFO has data)

To send a character...
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1) Wait for Tx_FIFO status to be NOT FULL
2) Write character to Tx_FIFO

Send pseudo-code:
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while (UART_STATUS != TX_FIFO_FULL) { };
TX_FIFO = my_char;

To receive a character...
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1) Wait for Rx_FIFO status to be VALID
2) Read a character from the Rx_FIFO

Receive pseudo-code:
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while (UART_STATUS != RX_FIFO_VALID) { };
my_char = RX_FIFO;